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smsc lan91c110 rev. b page 1 revision 1.0 (11-04-08) datasheet lan91c110 rev. b feast fast ethernet controller for pcmcia and generic 16-bit applications product features ? dual speed csma/cd engine (10 mbps and 100 mbps) ? compliant with ieee 802.3 100base-t specification ? supports 100base-tx, 100base-t4 ? 16 bit wide data path (i nto packet buffer memory) ? generic 16-bit system level interface easily adaptable to isa, pcmcia (16-bit cardbus), and various cpu system interfaces ? support for 16 and 8 bit cpu accesses ? asynchronous bus interface ? 128 kbyte external memory ? built-in transparent arbitr ation for slave sequential access architecture ? flat mmu architecture with symmetric transmit and receive structures and queues ? ieee-802.3 mii (media independent interface) compliant mac-phy interface running at nibble rate ? mii management serial interface ? ieee-802.3u full duplex capability ? 144 pin tqfp lead-free rohs compliant package (1.0 millimeter height) order number(s): LAN91C110-PU for 144 pin tqfp lead-free rohs compliant package
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 2 revision 1.0 (11-04-08) datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 3 revision 1.0 (11-04-08) datasheet table of contents chapter 1 general desc ription............................................................................................................ ................5 chapter 2 pin configuration .............................................................................................................. .................6 chapter 3 description of pin functions................................................................................................... ...........7 chapter 4 functional description ......................................................................................................... ............11 4.1 description of blocks.......................................................................................................... ............... 11 4.1.1 clock genera tor block .......................................................................................................... ...... 11 4.2 csma/cd block .................................................................................................................. .............. 11 4.2.1 dma block ...................................................................................................................... ............ 11 4.2.2 arbiter block.................................................................................................................. .............. 11 4.2.3 mmu block...................................................................................................................... ............ 12 4.2.4 biu block ...................................................................................................................... .............. 12 4.2.5 mac-phy interf ace block ........................................................................................................ .. 12 4.2.6 mii management inte rface block ................................................................................................ 1 3 chapter 5 data structures and registers .................................................................................................. .......15 5.1 packet format in buffer memory ................................................................................................. ..... 15 5.2 typical flow of events for tr ansmit (auto re lease = 0)................................................................... 37 5.3 typical flow of events for tr ansmit (auto re lease = 1)................................................................... 38 5.4 typical flow of ev ents for receive ............................................................................................. ...... 40 5.5 memory part itioning ............................................................................................................ .............. 46 5.6 interrupt ge neration ........................................................................................................... ............... 46 chapter 6 operational de scription........................................................................................................ ...........49 6.1 maximum guarant eed ratings* .................................................................................................... .... 49 6.2 dc electrical characteristics.................................................................................................. ........... 49 chapter 7 timing diagrams ................................................................................................................ ..............51 chapter 8 package ou tline ................................................................................................................ ................56 list of figures figure 2.1 ? pin configuration ................................................................................................. ..................... 6 figure 3.1 - lan91c11 0 block diagram........................................................................................... .......... 10 figure 3.2 - lan91c11 0 system diagram .......................................................................................... ....... 10 figure 4.1 - lan91c110 internal bl ock diagram with data path ............................................................... 14 figure 5.1 ? data packet format................................................................................................ ................ 15 figure 5.2 ? interr upt structure............................................................................................... .................... 33 figure 5.3 ? interrupt service routine ......................................................................................... ............... 41 figure 5.4 - rx intr ........................................................................................................... ....................... 42 figure 5.5 - tx intr........................................................................................................... ........................ 43 figure 5.6 - txempty intr (assumes auto release opt ion sele cted)...................................................... 44 figure 5.7 - drive send an d allocate routines.................................................................................. ......... 45 figure 5.8 ? interrupt generati on for transmit, re ceive, mmu.................................................................. 4 8 figure 7.1 - asynchro nous cycle - nads =0 ....................................................................................... ........ 51 figure 7.2 - asynchronou s cycle - us ing nads................................................................................... .... 51 figure 7.3 ? address lat ching for a ll modes .................................................................................... .......... 52
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 4 revision 1.0 (11-04-08) datasheet figure 7.4 - sram interface .................................................................................................... ................... 53 figure 7.5 - m ii interf ace..................................................................................................... ........................ 55 figure 8.1 - 144 pin tq fp package outlines..................................................................................... ........ 56 list of tables table 5.1 - internal i/o space mapping......................................................................................... ............... 18 table 8.1 ? 144 pin tq fp package pa rameters .................................................................................... ... 56
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 5 revision 1.0 (11-04-08) datasheet chapter 1 general description the lan91c110 is designed to facilitate the implementation of second generation fast ethernet pc card adapters and other non-pci connectivity products. the la n91c110 is a digital device that implements the media access control (mac) portion of the csma/cd protoc ol at 10 and 100 mbps, and couples it with a lean and fast data and control path system architecture to ensure that the cpu to packet ram data movement does not cause a bottleneck at 100 mbps. the lan91c110 implements a generic 16-bit host interf ace which is adaptable to a wide range of system buses and cpus. this makes the lan91c110 ideal for 10/100 fast ethernet implementations in systems based on system buses other than pci. total memory size is 128 kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding packets. the lan91c110 is software compatible with the lan9000 family of products in the default mode and can use existing lan9000 drivers (odi, ipx, and ndis) with minor modifications in 16 and 32 bit intel x86 based environments. memory management is handled using a unique paten ted mmu (memory managem ent unit) architecture and an internal 32-bit wide data path. this i/o m apped architecture can sustain back-to-back frame transmission and reception for superior data throug hput and optimal performance. it also dynamically allocates buffer memory in an effi cient buffer utilization scheme, reducing software tasks and relieving the host cpu from performing these housekeeping functions. the total memory size is 128 kbytes (external), equivalent to a total chip storage (transmi t and receive) of 64 outstanding packets. feast provides a flexible slave interface for easy connectivity with industry-standard buses. the host interface is ?isa-like? and is easily adapted to a wi de range of system and cpu buses such as isa, pcmcia, etc. an ieee-802.3 compliant media independent interface (mi i) provided on the network side of the lan91c110. the mii interface allows the use of a wide range of mii co mpliant physical layer (phy) devices to be used with the lan91c110. the lan91c110 also provides an interface to the two-line mii serial management protocol.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 6 revision 1.0 (11-04-08) datasheet chapter 2 pin configuration lan91c110 144 pin tqfp 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 vdd gnd xtal2 xtal1 vdd ncsout tx25 rx_er rx_dv gnd rx25 col100 crs100 rxd0 rxd1 rxd2 rxd3 txd0 txd1 txd2 txd3 txen100 nrwe0 rd7 rd6 rd5 rd4 gnd rd3 rd2 rd1 vdd rd0 rd15 rd14 nlnk vdd gnd rd8 ra12 ra4 ra3 gnd nrwe3 ra2 rd24 rd25 rd26 rd27 rd28 rd29 nrwe2 rd30 rd31 vdd rd16 rd17 rd18 rd19 rd20 gnd rd21 rd22 rd23 rd13 rd12 gnd rd11 rd10 vdd rd9 nrwe1 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 37 38 39 40 41 42 43 44 a9 a8 a7 a6 a5 a4 a3 a2 a1 gnd d8 d9 vdd d10 d11 d12 d13 d14 gnd d15 nads vdd ra16 ra14 ra15 ra9 ra10 ra8 ra11 vdd nroe ra7 gnd ra13 ra5 ra6 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 nwr reset gnd mclk aen auisel mdo mdi agnd n/c avdd a10 vdd nrd int0 gnd ardy d0 d1 d2 d3 gnd d4 d5 d6 nldev d7 nbe1 nbe0 gnd a15 a14 a13 a12 vdd a11 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 figure 2.1 ? pin configuration
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 7 revision 1.0 (11-04-08) datasheet chapter 3 description of pin functions 144 tqfp pin no. name symbol buffer type description 115-112, 110-100 address a[15:1] i input. used by lan91c110 for internal register selection. 138 address enable aen i input. used as an address qualifier. address decoding is only enabled when aen is low. 118, 117 nbe[1:0] i input. used during lan91c110 register accesses to determine the width of the access and the register(s) being accessed. 89, 91-95, 97-98, 119, 121-123, 125-128 data bus d[15:0] i/o8 bidirectional. 16-bit data bus used to access the lan91c110?s internal registers. data bus has weak internal pullups. supports direct connection to the system bus without external buffering. 135 reset reset is input. this input is not considered active unless it is active for at least 100ns to filter narrow glitches. 129 asynchro- nous ready ardy od16 open drain output. ardy may be used when interfacing asynchronous buses to extend accesses. its rising (access completion) edge is controlled by the xtal1 clock and, therefore, asynchronous to the host cpu or bus clock. note : asserted for 100 to 150ns for the appropriate no wait bit state in the configuration register. see the no wait bit description for complete information. 120 local device nldev o16 output. local device. this active low output is asserted when aen is low and a4-a15 decode to the lan91c110 address programmed into the high byte of the base address register. nldev* is a combinatorial decode of unlatched address and aen signals. 88 naddress strobe nads is input. address strobe. for systems that require address latching. the rising edge of nads indicates the latching moment of a[1:15] and aen. all lan91c110 internal functions of a[1:15] and aen are latched. 131 interrupt intr0 o4 output. the interrupt output is enabled by selecting the appropriate routing bits (int sel 1- 0) in the configuration register. 132 nread strobe nrd is input. used in asynchronous bus interfaces. 134 nwrite strobe nwr is input. used in asynchronous bus interfaces.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 8 revision 1.0 (11-04-08) datasheet 144 tqfp pin no. name symbol buffer type description 56-57, 60- 65, 46-48, 50-54, 35- 38, 40-42, 45, 25-28, 30-32, 34 ram data bus rd[31:0] i/o4 with pullups bidirectional. carries the local buffer memory read and write data. reads are always 32 bits wide. writes are controlled individually at the byte level. 86,84,85, 75,72,80, 82- 83,81, 77,74- 73, 71-70,67 ram address bus ra[16:2] o4 outputs. this bus specifies the buffer ram doubleword being accessed by the lan91c110. 78 nroe o4 output. active low signal used to read a doubleword from buffer ram. 24,44,58, 68 nrwe[3:0] o4 outputs. active low signals used to write any byte, word or dword in ram. 2 3 crystal 1 crystal 2 xtal1 xtal2 iclk an external 25 mhz crystal is connected across these pins. if a ttl clock is supplied instead, it should be connected to xtal1 and xtal2 should be left open. 1 nlink status nlnk i with pullup input. general purpose input port used to convey link status (ephsr bit 14). 139 aui select auisel o4 output. non volatile output pin. driven by aui select (config bit 8). 23 transmit enable mii txen100 o12 output to mii phy. envelope to 100 mbps transmission. 12 carrier sense mii crs100 i with pulldown input from mii phy. envelope of packet reception used for deferral and backoff purposes. 8 receive data valid rx_dv i with pulldown input from mii phy. envelope of data valid reception. used for receive data framing. 11 collision detect mii col100 i with pulldown input from mii phy. collision detection input. 18,19,21, 22 transmit data txd[3:0] o12 outputs. transmit data nibble to mii phy. 6 transmit clock tx25 i with pullup input. transmit cl ock input from mii. nibble rate clock (25 mhz). 10 receive clock rx25 i with pullup input. receive clock input from mii phy. nibble rate clock. 16-13 receive data rxd[3:0] i inputs. received da ta nibble from mii phy. 141 manage- ment data input mdi i with pulldown mii management data input. 140 manage- ment data output mdo o4 mii management data output. 137 manage- ment clock mclk o4 mii management clock.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 9 revision 1.0 (11-04-08) datasheet 144 tqfp pin no. name symbol buffer type description 7 receive error rx_er i with pulldown input. indicates a code error detected by phy. used by the lan91c110 to discard the packet being received. the error indication reported for this event is the same as a bad crc (receive status word bit 13). 5 nchip select output ncsout o4 output. chip select provided for mapping of phy functions into lan91c110 decoded space. active on accesses to lan91c110?s eight lower addresses when the bank selected is 7. 4,20,33,43,5 5,66,79, 87,96,111,13 3 power vdd +5v power supply pins. 144 analog power avdd +5v analog power supply pins. 9,17,29,39,4 9,59,69, 76,90,99, 116,124, 130,136, ground gnd ground pins. 142 analog ground agnd analog ground pin. buffer types o4 o utput buffer with 2 m a source and 4 m a sink o12 output buffer with 6ma source and 12ma sink od16 open drain buffer with 16ma sink i/o4 bidirectional bu ffer with 2ma source and 4ma sink i/o8 bidirectional bu ffer with 4ma source and 8ma sink is schmitt trigger (hysteresis: 250mv) i with pullup rated at 30ma i with pulldown rated at 30ma
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 10 revision 1.0 (11-04-08) datasheet figure 3.1 - lan91c110 block diagram figure 3.2 - lan91c110 system diagram address control data address control data system bus mii rd0-31 oe, we ra sram 32kx8 1 2 3 4 lan9 1 c1 1 0 feast 100base-t4 interface chip 100base-t4 1 0 0 base-tx interface logic/ 10base-t 100base-tx/ 1 0 base-t or bus interface unit arbiter memory management unit direct memory access media access control rd fifo wr fifo address data control ram 25 mhz 10/100 mb/s media independent interface
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 11 revision 1.0 (11-04-08) datasheet chapter 4 functional description 4.1 description of blocks 4.1.1 clock generator block 1. the xtal1 and xtal2 pins are to be connected to a 25 mhz 50 ppm crystal. 2. tx25 is an input clock. it will be the nibble rate of the particular phy connected to the mii (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 3. rx25 - this is the mii nibble rate receive clock us ed for sampling received data nibbles and running the receive state machine. (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 4.2 csma/cd block this is a 16 bit oriented block, with fully- independent transmit and receive logic. the data path in and out of the block consists of two 16-bit wide uni-directional fi fos interfacing the dma block. the dma port of the fifo stores 32 bits to exploit the 32 bit data path into memory, but the fifos themselves are 16 bit wide. the control path consists of a set of registers interfaced to the cpu via the biu. 4.2.1 dma block this block accesses packet memory on the csma/cd?s behalf, fetching transmit data and storing received data. it interfaces the csma/cd tran smit and receive fifos on one side, and the arbiter block on the other. to increase the bandwidth into memory, a 50 mhz clock is used by the dma block, and the data path is 32 bits wide. for example, during active reception at 100 mbps, the csma/cd block will write a word into the receive fifo every 160ns. the dma will read the fifo and accumulate two words on the output port to request a memory cycle from the arbiter every 320ns. the dma machine is able to support full duplex operation. independent receive and transmit counters are used. transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed. 4.2.2 arbiter block the arbiter block sequences accesses to packet ram requested by the biu and by the dma blocks. biu requests represent pipelined cpu acce sses to the data register, while dma requests represent csma/cd data movement. the external memory used is a 25ns sram. the arbiter is also responsible for controlling the nr we0-nrwe3 lines as a function of the bytes being written. read accesses are always 32 bit wide, and the arbiter steers the ap propriate byte(s) to the appropriate lanes as a function of the address.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 12 revision 1.0 (11-04-08) datasheet the cpu data path consists of two uni-directional fifo s mapped at the data register location. these fifos can be accessed in any combination of bytes, word, or doublewords. the arbiter will indicate 'not ready' whenever a cycle is initiated that cannot be satisfied by the present state of the fifo. 4.2.3 mmu block the hardware memory management unit allocates memory and transmit and receive packet queues. it also determines the value of the transmit and receive interrupt s as a function of the queues. the page size is 2k, with a maximum memory size of 128k. mir and mc r values are interpreted in 512 byte units. 4.2.4 biu block the bus interface unit can handle synchronous as well as asynchronous buses; different signals are used for each one. transparent latches are added on the address path using rising nads for latching. with isa, the read and write operations are controlled by the edges of nrd and nwr. ardy is used for notifying the system that it should extend the access cycle. the leading edge of ardy is generated by the leading edge of nrd or nwr while the trailing edge of ardy is controlled by the internal lan91c110 clock and, therefore, asynchronous to the bus. the biu is implemented using the following principles: 1. address decoding is based on the values of a15-a4 and aen. 2. address latching is performed by using transpar ent latches that are transparent when nads=0 and nrd=1, nwr=1 and latch on nads rising edge. 3. byte, word and doubleword accesses to all registers and data path are supported except a doubleword write to offset ch will only write th e bank select register (offset fh). 4. no bus byte swapping is implemented (no eight bit mode). 5. word swapping as a function of a1 is implemented for 16 bit bus support. 6. the asynchronous interface uses nrd and nwr strobe s. if necessary, ardy is negated on the leading edge of the strobe. the ardy trailing edge is controlled by clk. 4.2.5 mac-phy interface block for the mii interface, transmit data is clocked out using the tx25 clock input, while receive data is clocked in using rx25. in 100 mbps mode, the lan91c110 provides th e following interface signals to the phy: ? for transmission: txen100 txd0-3 tx25 ? for reception: rx_d v rx_er rxd0-3 rx25 ? for csma/cd state machines: crs100 col100 a transmission begins by txen100 going active (high), and txd0-txd3 having the first valid preamble nibble. txd0 carries the least significant bit of the nibble (that is the one that would go first out of the eph at 100 mbps), while txd3 carries the most significant bit of the nibble. txen100 and txd0-txd3 are clocked by the lan91c110 using tx25 rising edges. txen100 goes inactive at the end of the packet on the last nibble of the crc. during a transmission, col100 might become active to indicate a collision. col100 is asynchronous to the lan91c110?s clocks and will be synchronized internally to tx25.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 13 revision 1.0 (11-04-08) datasheet reception begins when rx_dv (receive data valid) is asserted. a preamble pattern or flag octet will be present at rxd0-rxd3 when rx_dv is activated. the lan91c110 requires no training sequence beyond a full flag octet for reception. rx_dv as well as rxd0-rxd3 are sampled on rx25 rising edges. rxd0 carries the least significant bit and rxd3 the most significant bit of the nibble. rx_dv goes inactive when the last valid nibble of the packet (crc) is presented at rxd0-rxd3. rx_er might be asserted during packe t reception to signal the lan91c110 that the present receive packet is invalid. the lan91c110 will discard the packet by treating it as a crc error. rxd0-rxd3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned cases. opening flag detection expec ts the 5dh pattern and will not reject the packet on non-preamble patterns. crs100 is used as a frame envelope signal for th e csma/cd mac state machines (deferral and backoff functions), but it is not used for receive framing func tions. crs100 is an asynchronous signal and it will be active whenever there is activity on the cable, including lan91c110 transmissions and collisions. the mii select bit in the config register must always be set for proper chip function. note that given the modular nature of the mii, tx25 and rx25 cannot be assumed to be free running clocks. the lan91c110 will not rely on the presence of tx25 and rx25 during reset and will use its own internal clock whenever a timeout on tx25 is detected. 4.2.6 mii management interface block phy management through the mii management interface is supported by the lan91c110 by providing the means to drive a tri-statable data output, a clock, and reading an input. timing and framing for each management command is to be generated by the cpu.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 14 revision 1.0 (11-04-08) datasheet 8-16 bit bus interface unit arbiter dma mmu ethernet protocol handler (eph) external sram wr fifo rd fifo control rx data tx data control control address data control control rxd[0-3] txd[0-3] control tx/rx fifo pointer control eeprom interface 32-bit data 32-bit data figure 4.1 - lan91c110 internal block diagram with data path
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 15 revision 1.0 (11-04-08) datasheet chapter 5 data structures and registers 5.1 packet format in buffer memory the packet format in memory is similar for the transmit and receive areas. the first word is reserved for the status word. the next word is used to specify the total number of bytes, and it is followed by the data area. the data area holds the packet itself. figure 5.1 ? data packet format transmit packet receive packet status word written by csma upon transmit completion (see status register) written by csma upon receive completion (see rx frame status word) byte count written by cpu written by csma data area written/modified by cpu written by csma control byte written by cpu to control odd/even data bytes written by csma; also has odd/even bit byte count - divided by two, it defines the total number of words including the status word, the byte count word, the data area and the control byte. reserved byte count (always even) status word data area last data byte (if odd) bit0 bit15 ram offset (decimal) 0 2 4 2046 max control byte last byte 1st byte 2nd byte
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 16 revision 1.0 (11-04-08) datasheet the receive byte count always appears as even; the oddfrm bit of the receive status word indicates if the low byte of the last word is relevant. the transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. data area - the data area starts at offset 4 of th e packet structure and can extend up to 2043 bytes. the data area contains six bytes of destination addr ess followed by six bytes of source address, followed by a variable-length number of bytes. on transmit, all bytes are provided by the cpu, including the source address. the lan91c110 does not insert its own source address. on receive, all bytes are provided by the csma side. the 802.3 frame length word (frame type in ethernet) is not interpreted by the lan91c110. it is treated transparently as data both for transmit and receive operations. control byte - for transmit packets the control byte is written by the cpu as: x x odd crc 0 0 0 0 odd - if set, indicates an odd number of bytes, with the la st byte being right before the control byte. if clear, the number of data bytes is even and the byte before the control byte is not transmitted. crc - when set, crc will be appended to the frame. this bit has only meaning if the nocrc bit in the tcr is set. for receive packets the control byte is written by the controller as: 0 1 odd 0 0 0 0 0 odd - if set, indicates an odd number of bytes, with the la st byte being right before the control byte. if clear, the number of data bytes is even and the byte before the control byte should be ignored. receive frame status word this word is written at the beginning of each receive frame in memory. it is not available as a register. high byte algn err brod cast bad crc odd frm toolng too short low byte hash value mult cast 5 4 3 2 1 0 algnerr - frame had alignment error. when mii sel=1 alignment error is set when badcrc=1 and an odd number of nibbles was received between sfd and rx_dv going inactive.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 17 revision 1.0 (11-04-08) datasheet brodcast - receive frame was broadcast. badcrc - frame had crc error, or rx_e r was asserted during reception. oddfrm - this bit when set indicates that the received frame had an odd number of bytes. toolng - frame length was longer than 802.3 maximum size (1518 bytes on the cable). tooshort - frame length was shorter than 802.3 minimum size (64 bytes on the cable). hash value - provides the hash value used to index the multicast registers. can be used by receive routines to speed up the group address search. the hash value consists of the six most significant bits of the crc calculated on the destination address, and maps into the 64 bit multicast table. bits 5,4,3 of the hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected. examples of the address mapping: address hash value 5-0 multicast table bit ed 00 00 00 00 00 0d 00 00 00 00 00 01 00 00 00 00 00 2f 00 00 00 00 00 000 000 010 000 100 111 111 111 mt-0 bit 0 mt-2 bit 0 mt-4 bit 7 mt-7 bit 7 multcast - receive frame was multicast. if hash value corresponds to a multicast table bit that is set, and the address was a multicast, the packet will pass address filt ering regardless of other filtering criteria. i/o space the base i/o space is spec ified by the power-up i/o base register default. to limit the i/o space requirements to 16 locations, the registers are assigned to different banks. the last word of the i/o area is shared by all banks and can be used to change the bank in use. registers are described using the following convention: offset name type symbol high byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x x x x x low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x x x offset - defines the address offset within the iobase where th e register can be accessed at, provided the bank select has the appropriate value. the offset specifies the address of the even byte (bits 0-7) or the address of the complete word. the odd byte can be accessed using address (offset + 1). some registers (like the interrupt ack., or like interrupt mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 18 revision 1.0 (11-04-08) datasheet regardless of the functional description, all registers can be accessed as doublewords, words or bytes. the default bit values upon hard reset are highlighted below each register. table 5.1 - internal i/o space mapping bank0 bank1 bank2 bank3 0 tcr config mmu command mt0-1 2 eph status base pnr mt2-3 4 rcr ia0-1 fifo ports mt4-5 6 counter ia2-3 pointer mt6-7 8 mir ia4-5 data mgmt a mcr - data revision c reserved (0) control interrupt rcv e bank select bank select bank select bank select a special bank (bank7) exis ts to support the addition of external registers. bank select register offset name type symbol e bank select register read/write bsr high byte 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 low byte bs2 bs1 bs0 x x x x x 0 0 0 bs2, bs1, bs0 determine the bank presently in use. this register is always accessible and is used to select the register bank in use. the upper byte always reads as 33h and can be used to help determine the i/o location of the lan91c110. the bank select register is always acce ssible regardless of the value of bs0-2. note: the bank select register can be accessed as a word at offset 0x0eh, or as a byte at offset 0x0fh. bank 7 has no internal registers other than the bank sele ct register itself. on va lid cycles where bank7 is selected (bs0=bs1=bs2=1), and a3=0, ncsout is activat ed to facilitate implementation of external registers. note: bank7 does not exist in lan91c9x devices. for backward s/w compatibility bank7 accesses should be done if the revision control register indicates the device is the lan91c110.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 19 revision 1.0 (11-04-08) datasheet bank 0 offset name type symbol 0 transmit control register read/write tcr this register holds bits programme d by the cpu to control some of the protocol transmit options. high byte swfdup reserved eph loop stp sqet fduplx reserved reserved nocrc 0 0 0 0 0 0 0 0 low byte pad_en reserved reserved reserved reserved forcol reserved txena 0 0 0 0 0 0 0 0 swfdup - enables switched full duplex mode. in this mode, transmit state machine is inhi bited from recognizing carrier sense, so deferrals will not occur. also inhibits collision coun t, therefore, the collision related status bits in the ephsr a re not valid (ctr_rol, latcol, sqet, 16col, mul col, and sngl col). uses col100 as flow control, limiting backoff and jam to 1 clock each before inter-frame gap, then retry will occur after ifg. if col100 is active during preamble, full preamble will be output before jam. when sw fdup is high, the values of fduplx and mon_csn have no effect. this bit should be low for non-mii operation. eph_loop - internal loopback at the eph block. serial data is internally looped back when set. defaults low. when eph_loop is high the following transmit outputs are forced inactive: txd0-txd3 = 0h, txen100 = txen = 0, txd = 1. the following and external inputs are blocked: crs=crs100=0, col=col100=0, rx_dv= rx_er=0. stp_sqet - stop transmission on sqet error. if set, stops and disables transmitter on sqe test error. does not stop on sqet error and transmits next frame if clear. defaults low. fduplx - when set the lan91c110 will cause frames to be re ceived if they pass the address filter regardless of the source for the frame. when clear the node will not receive a fr ame sourced by itself. this bit does not control the duplex mode operation, the duplex mode operation is controlled by the swfdup bit. nocrc - does not append crc to transmitted frames when set. allows software to insert the desired crc. defaults to zero, namely crc inserted. pad_en - when set, the lan91c110 will pad transmit frames shorter than 64 bytes with 00. for tx, cpu should write the actual byte count before padded by the lan91c110 to th e buffer ram, excludes the padded 00. when this bit is cleared, the lan91c110 does not pad frames. forcol - when set, the forcol bit will force a collision by not deferring deliberately. this bit is set and cleared only by the cpu. when txena is enabled with no packets in the queue and while the forcol bit is set, the lan91c110 will transmit a preamble pattern the next time a carrier is seen on the line. if a packet is queued, a preamble and sfd will be transmitted. this bit defaults low to normal operation. note : the latcol bit in the ephsr, setting up as a result of forcol, will reset txena to 0. in order to force another collision, txena mu st be set to 1 again. txena - transmit enabled when set. transmit is disabled if clear. when the bit is cleared the lan91c110 will complete the current transmission before stopping. when stopping due to an error, this bit is automatically cleared.
smsc lan91c110 rev. b page 20 revision 1.0 (11-04-08) datasheet bank 0 offset name type symbol 2 eph status register read only ephsr this register stores the status of the last transmitted frame. this register value, upon individual transmit packet completion, is stored as the first word in the memory area allo cated to the packet. packet interrupt processing should use the copy in memory as the register itself will be update d by subsequent packet transmissions. the register can be used for real time values (like txena and link ok). if txena is cleared the register holds the last packet completion status. high byte reserved link_ ok reserved ctr _rol exc _def reserved latcol reserved 0 -nlnk pin 0 0 0 0 0 0 low byte tx defr ltx brd sqet 16col ltx mult mul col sngl col tx_suc 0 0 0 0 0 0 0 0 link_ok - general purpose input port driven by nlnk pin invert ed. typically used for link test. a transition on the value of this bit generates an interrupt. ctr_rol - counter roll over. when set one or more 4 bit counters have reached maximum count (15). cleared by reading the ecr register. exc_def - excessive deferral. when set la st/ current transmit was deferred for more than 1518 * 2 byte times. cleared at the end of every packet sent. latcol - late collision detected on last transmit frame. if set a late collision was detected (later than 64 byte times into the frame). when detected the transmitter jams and turns it self off clearing the txena bit in tcr. cleared by setting txena in tcr. tx_defr - transmit deferred. when set, carrier was detected during the first 6.4 s of the inter frame gap. cleared at the end of every packet sent. ltx_brd - last transmit frame was a broadcast. set if frame was broadcast. cleared at the start of every transmit frame. sqet - signal quality error test. sqet bit is always se t after first transmit, except if swfdup=1. as a consequence, the stp_sqet bit in the tcr register cannot be set as it will always result in transmit fatal error. transmission stops and eph int is set if stp_sqet is in the tcr is also set when sqet is set. this bit is cl eared by setting txena high. 16col - 16 collisions reached. set when 16 collisions are de tected for a transmit frame. txena bit in tcr is reset. cleared when txena is set high. ltx_mult - last transmit frame was a multicast. set if frame was a multicast. cleared at the start of every transmit frame. mulcol - multiple collision detected for the last transmit frame. set when more than one collision was experienced. cleared when tx_suc is high at the end of the packet being sent.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 21 revision 1.0 (11-04-08) datasheet snglcol - single collision detected for the last transmit fr ame. set when a collision is detected. cleared when tx_suc is high at the end of the packet being sent. tx_suc - last transmit was successful. set if transmit completes without a fatal error. this bit is cleared by the start of a new frame transmission or when txena is set high. fatal errors are: ? 16 collisions (1/2 duplex mode only) ? sqet fail and stp_sqet = 1 (1/2 duplex mode only) ? late collision (1/2 duplex mode only) bank 0 offset name type symbol 4 receive control register read/write rcr high byte soft rst filt car abort_e nb reserved reserved reserved strip crc rxen 0 0 0 0 0 0 0 0 low byte reserved reserved reserved re served reserved almul prms rx_ abort 0 0 0 0 0 0 0 0 soft_rst - software-activated reset. active high. initiated by writing this bit high and terminated by writing the bit low. the lan91c110?s configuration is not preserved except for co nfiguration, base, and ia0-ia5 registers. eeprom is not reloaded after software reset. filt_car - filter carrier. when set filters leading edge of carrier sense for 12 bit times (3 nibble times). otherwise recognizes a receive frame as soon as carrier sens e is active. (does not filter rx dv on mii!) abort_enb - enables abort of receive when collision occu rs. defaults low. when set, the lan91c110 will automatically abort a packet being received when the appropriate collision input is this bit has no effect if the swfdup bit in the tcr is set. strip_crc - when set it strips the crc on received frames. when clear the crc is stored in memory following the packet. defaults low. rxen - enables the receiver when set. if cleared, complete s receiving current frame and then goes idle. defaults low on reset. almul - when set accepts all multicast frames (frames in which the first bit of da is '1'). when clear accepts only the multicast frames that match the multicast table setting. defaults low. prms - promiscuous mode. when set receiv es all frames. does not receive its ow n transmission unless it is in full duplex! rx_abort - this bit is set if a receiv e frame was aborted due to length longer than 2k bytes. the frame will not be received. the bit is cleared by reset or by the cpu writing it low. reserved - must be 0.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 22 revision 1.0 (11-04-08) datasheet bank 0 offset name type symbol 6 counter register read only ecr counts four parameters for mac statistics. when any counter reaches 15 an interrupt is issued. all counters are cleared when reading the register and do not wrap around beyond 15. high byte number of exc. deffered tx number of deffered tx 0 0 0 0 0 0 0 0 low byte multiple collision count single collision count 0 0 0 0 0 0 0 0 each four bit counter is incremented every time the corr esponding event, as defined in the eph status register bit description, occurs. note that the counters can only increment once per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counters . for example if a packet is successfully transmitted after one collision the single collision count field is incremented by one. if a packet experiences between 2 to 16 collisions, the multiple collision count field is incremented by one. if a packet experiences deferral the number of deferred tx field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. the counter register facilitates maintaining statistics in the auto release mode where no transmit interrupts are generated on successful transmissions. reading the register in the transmit service routine will be enough to maintain statistics. bank 0 offset name type symbol 8 memory information register read only mir high byte free memory available (in bytes * 256 * m) 1 1 1 1 1 1 1 1 low byte memory size (in bytes *256 * m) 1 1 1 1 1 1 1 1 free memory available - this register can be read at any time to determine the amount of free memory. the register defaults to the memory size upon reset or upon the reset mmu command. memory size - this register can be read to determine the total memory size. all memory related information is represented in 256 * m byte units, where the multiplier m is determined by the mcr upper byte. these register default to ffh, which should be interpreted as 256.
smsc lan91c110 rev. b page 23 revision 1.0 (11-04-08) datasheet bank 0 offset name type symbol a memory configuration register lower byte - read/write upper byte - read only mcr high byte memory size multiplier 0 0 1 1 0 1 0 1 low byte memory reserved for transmit (in bytes * 256 * m) 0 0 0 0 0 0 0 0 memory reserved fo r transmit - programming this value allows the host cpu to reserve memory to be used later for transmit, limiting the amount of memory that rece ive packets can use. when programmed for zero, the memory allocation between transmit and receive is completely dynamic. when programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free memory is less or equal to the programmed value. this regist er defaults to zero upon reset. it is not affected by the reset mmu command. the value written to the mcr is a reserved memory spac e in addition to any memory currently in use. if the memory allocated for transmit plus the re served space for transmit is required to be constant (rather than grow with transmit allocations) the cpu should update the value of this register after allocating or releasing memory. the contents of the mir as well as the low byte of the mcr are specified in units of 256 * m bytes, where m is the memory size multiplier. m=2 for the lan91c110. a value of 04h in the lower byte of the mcr is equal to one 2k page (4 * 256 *2 = 2k); since memory must be reserved in multiples of pages, bits 0 and 1 of the mcr should be written to 1 only when the entire memory is being reserved for transmit (i.e., low byte of mcr = ffh). bank1 offset name type symbol 0 configuration register read/write cr the configuration register holds bits that define the adap ter configuration and are not expected to change during run- time. this register is part of the eeprom saved setup. high byte mii select reserved no wait reserved full step reserved aui select 1 0 1 0 0 0 0 0 low byte 1 reserved reserved int sel1 int sel0 1 0 1 1 0 0 0 1
smsc lan91c110 rev. b page 24 revision 1.0 (11-04-08) datasheet mii select - used to select the network interface port. when set, the lan91c110 will use its mii port and interface a phy device at the nibble rate. this bit must always be set for proper chip function. no wait - when set, does not request additional wait states. an ex ception to this are accesses to the data register if not ready for a transfer. when clear, negates ardy for two to three clocks on any cycle to the lan91c110. full step - reserved aui select - this bit is a general purpose output port. its value drives pin auisel and can be used as a general purpose non-volatile configuration pin. defaults low. reserved - must be 0. int sel1-0 - used to select interrupt pin. the bits must re main 00 for the interrupt pin to be asserted for interrupt indication. all other bit combinations are undefined. bank 1 offset name type symbol 2 base address register read/write bar this register holds the i/o address decode option chosen for the lan91c110. is not usually modified during run-time. high byte a15 a14 a13 a9 a8 a7 a6 a5 0 0 0 1 1 0 0 0 low byte reserved 1 0 0 0 0 0 0 0 1 a15 - a13 and a9 - a5 - these bits are compared against th e i/o address on the bus to determine the iobase for the lan91c110?s registers. the 64k i/o space is fully decoded by the lan91c110 down to a 16 location space, therefore the unspecified address lines a4, a10, a11 and a12 must be all zeros. the i/o base decode defaults to 300h (namely, the high byte defaults to 18h). reserved - must be 0.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 25 revision 1.0 (11-04-08) datasheet bank 1 offset name type symbol 4 through 9 individual address registers read/write iar these registers are required to be written by the host following power-up and hardware reset. for pc card designs, the cis contains the node address. the s/w driver must load that address into these registers. the registers are modified by the software driver. bit 0 of individual address 0 register corresponds to the first bit of the address on the cable. low byte address 0 0 0 0 0 0 0 0 0 high byte address 1 0 0 0 0 0 0 0 0 low byte address 2 0 0 0 0 0 0 0 0 high byte address 3 0 0 0 0 0 0 0 0 low byte address 4 0 0 0 0 0 0 0 0 high byte address 5 0 0 0 0 0 0 0 0 bank 1 offset name type symbol a reserved.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 26 revision 1.0 (11-04-08) datasheet bank 1 offset name type symbol c control register read/write ctr high byte reserved rcv_ bad reserved 1 auto release reserved 1 reserved 0 0 0 1 0 0 1 0 low byte le enable cr enable te enable 1 reserved reserved reserved reserved 0 0 0 1 0 0 0 0 rcv_bad - when set, bad crc packets are received. when clear bad crc packets do not generate interrupts and their memory is released. auto release - when set, transmit pages are released by tr ansmit completion if the transmission was successful (when tx_suc is set). in that case there is no status wo rd associated with its packet number, and successful packet numbers are not even written into the tx completion fi fo. a sequence of transmit packets will generate an interrupt only when the sequence is completely transmitted (tx empty int will be set), or when a packet in the sequence experiences a fatal error (tx int will be set). upon a fatal error txena is cleared and the transmission sequence stops. the packet number that failed, is present in the fifo ports register, and its pages are not released, allowing the cpu to restart the sequence after corrective action is taken. le enable - link error enable. when set it enables the link _ok bit transition as one of the interrupts merged into the eph int bit. clearing the le enable bit after an eph int interrupt, caused by a link_ok transition, will acknowledge the interrupt. le enable defaults low (disabled). cr enable - counter roll over enable. when set, it enables the ctr_rol bit as one of the interrupts merged into the eph int bit. reading the counter register after an eph int interrupt caused by a count er rollover, will acknowledge the interrupt. cr enable defaults low (disabled). te enable - transmit error enable. when set it enables tr ansmit error as one of the interrupts merged into the eph int bit. an eph int interrupt caused by a transmitter error is acknowledged by setting txena bit in the tcr register to 1 or by clearing the te enable bit. te enable defaults low (disabled). transmit error is any condition that clears txena with tx_suc staying low as described in the ephsr register. reserved 2-0: these reserved bits must always be written to as zero(0).
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 27 revision 1.0 (11-04-08) datasheet bank2 offset name type symbol 0 mmu command register write only busy bit readable mmucr this register is used by the cpu to control the memory allocation, de-allocation, tx fifo and rx fifo control. the three command bits determine the comm and issued as described below: high byte low byte command reserved reserved n2 n1 n0/busy x y z 0 command set: xyz 000 0) noop - no operation 001 1) allocate memory for tx - n2, n1, n0 defines the amount of memory requested as (value + 1) * 256 bytes. namely n2, n1, n0 = 1 will request 2 * 256 = 512 bytes. a shift-based divide by 256 of the packet length yields the appropriate value to be used as n2, n1, n0. immediately generates a completion code at the allocation result register. can optionally gener ate an interrupt on successful completion. n2, n1, n0 are ignored by the lan91c110 but should be implemented in lan91c110 software drivers for lan9000 compatibility. 010 2) reset mmu to initial state - frees all memory allocations, clears relevant interrupts, resets packet fifo pointers. 011 3) remove frame from top of rx fifo - to be is sued after cpu has completed processing of present receive frame. this command removes the receive packe t number from the rx fifo and brings the next receive frame (if any) to the rx area (output of rx fifo). 100 4) remove and release top of rx fifo - like 3) but also releases all memory used by the packet presently at the rx fifo output. the mmu bus y time after issuing remove and release command depends on the time when the busy bit is cleared. the time from issuing remove and release command on the last receive packet to the time when receive fifo is empty depends on rx int bit turning low. an alternate approach can be checking the read rx fifo register. 101 5) release specific packet - frees all pages allocated to the packet specified in the packet number register. should not be used for frames pending tran smission. typically used to remove transmitted frames, after reading their completion status. can be used following 3) to release receive packet memory in a more flexible way than 4). 110 6) enqueue packet number into tx fifo - this is the normal method of transmitting a packet just loaded into ram. the packet number to be enqueued is taken from the packet number register. 111 7) reset tx fifos - this command will reset both tx fifos: the tx fifo holding the packet numbers awaiting transmission and the tx completion fifo. this command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. the reset tx fifos command should only be used when the transmitter is dis abled. unlike the reset mmu command, the reset tx fifos does not release any memory.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 28 revision 1.0 (11-04-08) datasheet note 1: bits n2,n1,n0 bits are ignored by the lan91c110 but should be used for command 0 to preserve software compatibility with the lan91c92 and future devices. they should be zero for all other commands. note 2: when using the reset tx fifos command, the cpu is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. packet number s in the completion fifo can be read via the fifo ports register before issuing the command. note 3: mmu commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it. command sequencing a second allocate command (command 1) should not be iss ued until the present one has completed. completion is determined by reading the failed bit of the allocation result register or through the allocation interrupt. a second release command (commands 4, 5) should not be issued if the previous one is still being processed. the busy bit indicates that a release command is in progress. after issuing command 5, the contents of the pnr should not be changed until busy goes low. after issuing command 4, command 3 should not be issued until busy goes low. busy bit - readable at bit 0 of the mmu command register addre ss. when set indicates that mmu is still processing a release command. when clear, mmu has already completed last release command. busy and failed bits are set upon the trailing edge of command. bank 2 offset name type symbol 2 packet number register read/write pnr reserved reserved packet number at tx area 0 0 0 0 0 0 0 0 packet number at tx area - the value written into this register determines which packet number is accessible through the tx area. some mmu commands use the number stored in this register as the packet number parameter. this register is cleared by a reset or a reset mmu command. offset name type symbol 3 allocation result register read only arr this register is updated upon an allocate memory mmu command. failed reserved allo cated packet number 1 0 0 0 0 0 0 0 failed - a zero indicates a successful allocation completion. if the allocation fails the bit is set and only cleared when the pending allocation is satisfied. defaults high upon reset an d reset mmu command. for polling purposes, the alloc_int in the interrupt status register should be used because it is synchronized to the read operation. sequence:
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 29 revision 1.0 (11-04-08) datasheet 1. allocate command 2. poll alloc_int bit until set 3. read allocation result register allocated packet number - packet number associated with the last memory allocation request. the value is only valid if the failed bit is clear. note : for software compatibility with future versions, the value read from the arr after an allocation request is intended to be written into the pnr as is, without masking higher bits (provided failed = 0). bank 2 offset name type symbol 4 fifo ports register read only fifo this register provides access to the read ports of the receive fifo and the transmit completion fifo. the packet numbers to be processed by the interrupt serv ice routines are read from this register. high byte rempty 0 rx fifo packet number 1 0 0 0 0 0 0 0 low byte tempty 0 tx fifo packet number 1 0 0 0 0 0 0 0 rempty - no receive packets queued in the rx fifo. for pol ling purposes, uses the rcv_int bit in the interrupt status register. top of rx fifo packet number - packet number presently at the output of the rx fifo. only valid if rempty is clear. the packet is removed from the rx fifo using mmu commands 3) or 4). tempty - no transmit packets in completion queue. for po lling purposes, uses the tx_int bit in the interrupt status register. tx fifo packet number - packet number presently at the output of the tx fifo. only valid if tempty is clear. the packet is removed when a tx int acknowledge is issued. note: for software compatibility with future versions, the value r ead from each fifo register is intended to be written into the pnr as is, without masking higher bits (pro vided tempty and rempty = 0 respectively).
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 30 revision 1.0 (11-04-08) datasheet bank 2 offset name type symbol 6 pointer register read/write not empty is a read only bit ptr high byte rcv auto incr. read reserved not empty pointer high 0 0 0 0 0 0 0 0 low byte pointer low 0 0 0 0 0 0 0 0 pointer register - the value of this register determines the address to be accessed within the transmit or receive areas. it will auto-increment on accesses to the data register when auto incr. is set. the increment is by one for every byte access, by two for every word access, and by four for every double word access. when rcv is set the address refers to the receive area and uses the output of rx fifo as the packet number, when rcv is clear the address refers to the transmit area and uses the packet number at the packet number register. read - determines the type of access to follow. if the read bi t is high the operation intended is a read. if the read bit is low the operation is a write. loading a new pointer value, with the read bit high, generates a pre-fetch into the data register for read purposes. readback of the pointer will indicate the value of the address last accessed by the cpu (rathe r than the last pre-fetched). this allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted. the pointer register should not be loaded until the data register fifo is empty. the not empty bit of this register can be read to determine if the fifo is empty. on r eads, if iochrdy is not connected to the host, the data register (ardy) should not be read before 370ns after the pointer was loaded to allow the data register fifo to fill. if the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last. reserved ? must be 0. not empty - when set indicates that the write data fifo is not empty yet. the cpu can verify that the fifo is empty before loading a new pointer value. this is a read only bit. note: if auto incr. is not set, the pointer must be loaded with a dword aligned value. bank 2 offset name type symbol 8 through bh data register read/write data data high x x x x x x x x data low x x x x x x x x
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 31 revision 1.0 (11-04-08) datasheet data register - used to read or write the data buffer byte/word presently addressed by the pointer register. this register is mapped into two uni-directional fifos that allow moving words to and from the lan91c110 regardless of whether the pointer address is even, odd or dword aligned. data goes through the write fifo into memory, and is pre- fetched from memory into the read fifo. if byte accesses are used, the appropriate (next) byte can be accessed through the data low or data high registers. the order to and from the fifo is preserved. byte word accesses can be mixed on the fly in any order. this register is mapped into two consecutive word locations. the data register is accessible at any address in the 8 through ah range, while the number of bytes being transfe rred is determined by a1 and nbe0-nbe. the fifos are 12 bytes each. bank 2 offset name type symbol c interrupt status register read only ist reserved eph int rx_ovrn int alloc int tx empty int tx int rcv int 0 0 0 0 0 1 0 0 offset name type symbol c interrupt acknowledge register write only ack reserved rx_ovrn int tx empty int tx int offset name type symbol d interrupt mask register read/write msk reserved eph int mask rx_ovrn int mask alloc int mask tx empty int mask tx int mask rcv int mask 0 0 0 0 0 0 0 0 this register can be read and written as a word or as two individual bytes. the interrupt mask register bits enable the appropriate bits when high and disabl e them when low. a mask bit being set will cause a hardware interrupt. note : the bit 7 mask must never be written high (1).
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 32 revision 1.0 (11-04-08) datasheet reserved ? must be 0. eph int - set when the ethernet protocol handler section indi cates one out of various possible special conditions. this bit merges exception type of interrupt sour ces, whose service time is not critical to the execution speed of the low level drivers. the exact nature of the interrupt can be obtained from the eph status register (ephsr), and enabling of these sources can be done via the control register. the possible sources are: 1. link - link test transition 2. ctr_rol - statistics counter roll over 3. txena cleared - a fatal transmit error occurred forcing tx ena to be cleared. tx_suc will be low and the specific reason will be reflected by the bits: 3.1) sqet - sqe error 3.2) lost carr - lost carrier 3.3) latcol - late collision 3.4) 16col - 16 collisions any of the above interrupt sources can be masked by the appropriate enable bits in the control register. 1) le enable (link error enable), 2) cr enable (counter ro ll over), 3) te enable (transmit error enable) eph int will only be cleared by the following methods: 1. clearing the le enable bit in the control register if an eph interrupt is caused by a link_ok transition. 2. reading the counter register if an eph interrupt is caused by statistics counter roll over. 3. setting txena bit high if an eph interrupt is caused by any of the fatal transmit error listed above (3.1 to 3.5). rx_ovrn int - set when 1) the receiver aborts due to an ov errun due to a failed memory allocation, 2) the receiver aborts due to a packet length of greater than 2k bytes, or 3) the receiver aborts due to the rcv discrd bit in the rcv register set. the rx_ovrn int bit latches the condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the rx_ovrn int bit set. alloc int - set when an mmu request for tx ram pages is su ccessful. this bit is the complement of the failed bit in the allocation result register. the alloc int bit is cleared by the mmu when the next allocation request is processed or allocation fails. tx empty int - set if the tx fifo goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. this bit latches the empty c ondition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the tx empt y int bit set. if a real time reading of the fifo empty is desired, the bit should be first cleared and then read. the tx_empty mask bit should only be set after the following steps: 1. a packet is enqueued for transmission 2. the previous empty condition is cleared (acknowledged) tx int - set when at least one packet transmission was completed or any of the below transmit fatal errors occurs: 1. sqet - sqe error 2. lost carr - lost carrier 3. latcol - late collision 4. 16col - 16 collisions the first packet number to be serviced can be read from the fifo ports regist er. the tx int bit is always the logic complement of the tempty bit in the fifo ports register. after servicing a packet number, its tx int interrupt is removed by writing the interrupt acknowl edge register with the tx int bit set. rcv int - set when a receive interrupt is generated. the firs t packet number to be serviced can be read from the fifo ports register. the rcv int bit is always the logic comp lement of the rempty bit in the fifo ports register. receive interrupt is cleared when rx fifo is empty.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 33 revision 1.0 (11-04-08) datasheet figure 5.2 ? interrupt structure tx fifo empty dq s nq intack1 dq s nq intack2 dq s nq intack4 rx_ovrn nwrack tx complete fatal tx error sqet lost carr latcol 16col interrupt status register 76543210 nrdist interrupt mask register 76543210 oe noe edge detector on link err lemask ctr-rol crmask temask txena tx_svc ephsr interrupts merged into eph int allocation failed rx_ovrn int eph int alloc int tx empty int tx int rcv int int rcv fifo not empty d[7:0] d[15:8] data bus d[15:0] main interrupts
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 34 revision 1.0 (11-04-08) datasheet bank3 offset name type symbol 0 through 7 multicast table read/write mt low byte multicast table 0 0 0 0 0 0 0 0 0 high byte multicast table 1 0 0 0 0 0 0 0 0 low byte multicast table 2 0 0 0 0 0 0 0 0 high byte multicast table 3 0 0 0 0 0 0 0 0 low byte multicast table 4 0 0 0 0 0 0 0 0 high byte multicast table 5 0 0 0 0 0 0 0 0 low byte multicast table 6 0 0 0 0 0 0 0 0 high byte multicast table 7 0 0 0 0 0 0 0 0 the 64 bit multicast table is used for group address filtering. the hash value is defined as the six most significant bits of the crc of the destination addresses. the three msb's determine the register to be used (mt0-mt7), while the other three determine the bit within the register. if the appropriate bit in the table is set, the packet is received. if the almul bit in the rcr register is set, all multicast addr esses are received regardless of the multicast table values. hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the search time significantly. with the proper memory structure, the search is limited to comparing only the multicast addresses th at have the actual hash value in question.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 35 revision 1.0 (11-04-08) datasheet bank 3 offset name type symbol 8 management interface read/write mgmt high byte fltst msk_ crs100 0 0 1 1 0 0 1 1 low byte mdoe mclk mdi mdo 0 0 1 1 0 0 mdi pin 0 fltst - facilitates the inclusion of packet forwarding information on the receive packet memory structure. when 0, rd0- rd7 is always driven. when 1, rd0-rd7 is floated dur ing receive frame status word writes (ra2-ra16=0, rcvdma=1, nrwe0-nrwe3=0). msk_crs100 - disables crs100 detection during transmit in half duplex mode (swfdup=0). mdo - mii management output. the value of this bit drives the mdo pin. mdi - mii management input. the value of the mdi pin is readable using this bit. mdclk - mii management clock. the value of this bit drives the mdclk pin. mdoe - mii management output enable. when high pin mdo is driven, when low pin mdo is tri-stated. the purpose of this interface, along with the corresponding pins is to implement mii phy management in software. bank 3 offset name type symbol a revision register read only rev high byte 0 0 1 1 0 0 1 1 low byte chip rev 1 0 0 1 0 0 0 0 chip - chip id. can be used by software drivers to identify the device used. rev - revision id. incremented for each revision of a given device.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 36 revision 1.0 (11-04-08) datasheet chip id value device 3 lan91c90/lan91c92 4 lan91c94 5 lan91c95 4* lan91c96 7 lan91c100 8 lan91c100fd 9 lan91c110 *note: shares the chip id with the lan91c94. distinction is made by the revision id. revision id of 6 or higher represents the lan91c96. offset name type symbol c rcv register read/write rcv high byte 0 0 0 0 0 0 0 0 low byte rcv discrd reserved reserved mbo mbo mbo mbo mbo 0 0 0 1 1 1 1 1 rcv discrd - set to discard a packet being received. will discard packets only in the process of being received. when set prior to the end of receive packet, bit 4 (rxovrn) of the interrupt status register will be set to indicate that the packet was discarded. otherwise, the packet will be received normally and bit 0 set (rcvint) in the interrupt status register. rcv discrd is self clearing. mbo ? must be 1. bank7 offset name type symbol 0 through 7 external registers ncsout is driven low by the lan91c110 when a valid access to the external register range occurs. high byte external r/w register low byte external r/w register
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 37 revision 1.0 (11-04-08) datasheet cycle ncsout lan91c110 data bus aen=0 a3=0 a4-15 matches i/o base bank select = 7 driven low. transparently latched on nads rising edge. ignored on writes. tri-stated on reads. bank select = 4,5,6 high ignore cycle. otherwise high normal lan91c110 cycle. 5.2 typical flow of events for transmit (auto release = 0) s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (ntcr) bit and of the deferral process (1/2 duplex mode only) state. 6 a) upon transmit completion the first word in memory is written with the status word. the packet number is moved from the tx fifo into the tx completion fifo. interrupt is generated by the tx completion fifo being not empty. b) if a tx failure occurs on any packets, tx int is generated and txena is cleared, transmission sequence stops. the packet number of the failure packet is presented at the tx fifo ports register. 7 a) service interrupt - read interrupt status register. if it is a transmit interrupt, read the tx fifo packet number from the fifo ports register. write the packet number into the packet number register. the corresponding status word is now readable from memory. if status word shows successful transmission, issue release
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 38 revision 1.0 (11-04-08) datasheet s/w driver mac side packet number command to free up the memory used by this packet. remove packet number from completion fifo by writing tx int acknowledge register. b) option 1) release the packet. option 2) check the transmit status in the eph status register, write the packet number of the current packet to the packet number register, re-enable txena, then go to step 4 to start the tx sequence again. 5.3 typical flow of events for transmit (auto release = 1) s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (ntcr) bit and of the deferral process (1/2 duplex mode only) state. 6 transmit pages are released by transmit completion. 7 a) the mac generates a txempty interrupt upon a completion of a sequence of enqueued packets. b) if a tx failure occurs on any packets, tx int is generated and txena is cleared, transmission sequence stops. the packet number of the failure packet is presented at the tx fifo ports register. 8 a) service interrupt ? read interrupt status register, exit the interrupt service routine. b) option 1) release the packet.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 39 revision 1.0 (11-04-08) datasheet s/w driver mac side option 2) check the transmit status in the eph status register, write the packet number of the current packet to the packet number register, re-enable txena, then go to step 4 to start the tx sequence again.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 40 revision 1.0 (11-04-08) datasheet 5.4 typical flow of events for receive s/w driver mac side 1 enable reception - by setting the rxen bit. 2 a packet is received with matching address. memory is requested from mmu. a packet number is assigned to it. additional memory is requested if more pages are needed. 3 the internal dma logic generates sequential addresses and writes the receive words into memory. the mmu does the sequential to physical address translation. if overrun, packet is dropped and memory is released. 4 when the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. byte count is placed at the second word. if the crc checks correctly the packet number is written into the rx fifo. the rx fifo, being not empty, causes rcv int (interrupt) to be set. if crc is incorrect the packet memory is released and no interrupt will occur. 5 service interrupt - read the interrupt status register and determine if rcv int is set. the next receive packet is at receive area. (its packet number can be read from the fifo ports register). the software driver can process the packet by accessing the rx area, and can move it out to system memory if desired. when processing is complete the cpu issues the remove and release from top of rx command to have the mmu free up the used memory and packet number.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 41 revision 1.0 (11-04-08) datasheet figure 5.3 ? interrupt service routine isr save bank select & address ptr registers mask smc91c100fd interrupts read interrupt register call tx intr or txempty intr tx intr? get next tx rx intr? ye s no no yes call rxintr alloc intr? no yes write allocated pkt # into packet number reg. write ad ptr reg. & copy data & source address enqueue packet packet available for transmission? ye s n o call allocate eph intr? no ye s call eph intr set "ready for packet" flag return buffers to upper layer disable allocation interrupt mask restore address pointer & bank select registers unmask smc91c100fd interrupts exit isr
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 42 revision 1.0 (11-04-08) datasheet rx intr write ad. ptr. reg. & read word 0 from ram destination multicast? read words 2, 3, 4 from ram for address filtering address filtering pass? status word ok? do receive lookahead get copy specs from upper ye s no ye s no no ye s layer okay to copy? copy data per upper layer specs issue "remove and release" command return to isr no yes figure 5.4 - rx intr
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 43 revision 1.0 (11-04-08) datasheet write into packet number register tx status ok? tx intr save pkt number register read txdone pkt # from fifo ports reg. immediately issue "release" command acknowledge txintr read tx int again return to isr no ye s read status word from ram update statistics re-enable txena update variables tx int = 0? restore packet number ye s no write address pointer register figure 5.5 - tx intr
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 44 revision 1.0 (11-04-08) datasheet txempty intr write acknowledge reg. with txempty bit set read txempty & tx intr acknowledge txintr re-enable txena return to isr issue "release" command restore packet number txempty = 0 & txint = 0 (waiting for completion) txempty = x & txint = 1 (transmission failed) txempty = 1 & txint = 0 (everything went through successfully) read pkt. # register & save write address pointer register read status word from ram update statistics update variables figure 5.6 - txempty intr (assumes auto release option selected)
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 45 revision 1.0 (11-04-08) datasheet figure 5.7 - drive send and allocate routines allocate issue "allocate memory" command to mmu read interrupt status register enqueue packet set "ready for packet" flag return copy remaining tx data packet into ram return buffers to upper layer write allocated packet into packet # register write address pointer register copy part of tx data packet into ram write source address into proper location store data buffer pointer clear "ready for packet" flag enable allocation interrupt allocation passed? ye s n o driver send choose bank select register 2 call allocate exit driver send read allocation result register
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 46 revision 1.0 (11-04-08) datasheet 5.5 memory partitioning unlike other controllers, the lan91c110 does not re quire a fixed memory partitioning between transmit and receive resources. the mmu allocates and de-allocates memory upon different events. an additional mechanism allows the cpu to prevent the receive process from starving the transmit memory allocation. memory is always requested by the side that needs to write into it, that is: the cpu for transmit or the mac for receive. the cpu can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand. furthermore, the receive process requests will be dependent on network traffic, in pa rticular on the arrival of broadcast and multicast packets that might not be for the no de, and that are not subject to upp er layer software flow control. in order to prevent unwanted traffic from using too much memory, the cpu can program a "memory reserved for transmit" parame ter. if the free memory falls below the "memory rese rved for transmit" value, mmu requests from the mac block will fail and the packets will overrun and be ignored. whenever enough memory is released, packets can be received ag ain. if the reserved value is too large, the node might lose data which is an abnormal condition. if t he value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. note that with the memory management built into the lan91c110, the cpu can dynamically program this parameter. for instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory). whenever the driver needs to burst transmissions it can reduce the receive memory allocation. the driver program the parameter as a function of the following variables: 1. free memory (read only register) 2. memory size (read only register) the reserved memory value can be changed on the fl y. if the memory reserved for tx value is increased above the free memory, receive packets in progress are still received, but no new packets are accepted until the free memory increases above t he memory reserved value. 5.6 interrupt generation the interrupt strategy for the transmit and receive pr ocesses is such that it does not represent the bottleneck in the transmit and receive queue managemen t between the software driver and the controller. for that purpose there is no regi ster reading necessary before the ne xt element in the queue (namely transmit or receive packet) can be handled by the c ontroller. the transmit and receive results are placed in memory. the receive interrupt will be generated when the re ceive queue (fifo of packets) is not empty and receive interrupts are enabled. this allows the interr upt service routine to process many receive packets without exiting, or one at a time if the isr ju st returns after processing and removing one. there are two types of transmit interrupt strategies: 1. one interrupt per packet. 2. one interrupt per sequence of packets. the strategy is determined by how the transmit interrupt bits and the auto release bit are used. tx int bit - set whenever the tx completion fifo is not empty. tx empty int bit - set whenever the tx fifo is empty. auto release - when set, successful transmit packets are not written into completion fifo, and their memory is released automatically.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 47 revision 1.0 (11-04-08) datasheet 1. one interrupt per packet: enable tx int, set auto release=0. the software driver can find the completion result in memory and process the interrupt one packet at a time. depending on the completion code the driver will take different acti ons. note that the transmit process is working in parallel and other transmissions might be taking pl ace. the lan91c110 is virtually queuing the packet numbers and their status words. in this case, the transmit interrupt service routin e can find the next packet number to be serviced by reading the tx fifo packet number at the fifo port s register. this eliminates the need for the driver to keep a list of packet numbers being trans mitted. the numbers are queued by the lan91c110 and provided back to the cpu as their transmission completes. 2. one interrupt per sequence of packets: enable tx empty int and tx int, set auto release=1. tx empty int is generated only afte r transmitting the last packet in the fifo. tx int will be set on a fatal transmit error allowing the cpu to know that the transmit process has stopped and therefore the fi fo will not be emptied. this mode has the advantage of a sm aller cpu overhead, and faster memory de-allocation. note that when auto release=1 the cpu is not provided with the packet numbers that completed successfully. note : the pointer register is shared by any process accessing the lan91c110 memory. in order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt. typically there would be three processes using the pointer: 1. transmit loading (sometimes interrupt driven) 2. receive unloading (interrupt driven) 3. transmit status readi ng (interrupt driven). 1) and 3) also share the usage of the packet number register. therefore saving and restoring the pnr is also required from interrupt service routines.
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 48 revision 1.0 (11-04-08) datasheet t x f i f o t x c o m p l e t i o n f i f o r x f i f o c s m a / c d l o g i c a l a d d r e s s p a c k e t # m m u p h y s i c a l a d d r e s s r a m cpu address csma address rx packet number rx fifo pa c k e t n u m b e r packet number register pac k # o u t m.s. bit only 'empty' 'not empty' tx done packet number 'not empty' interrupt status register rcv int tx empty int tx int alloc int two options figure 5.8 ? interrupt generation for transmit, receive, mmu
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 49 revision 1.0 (11-04-08) datasheet chapter 6 operational description 6.1 maximum guaranteed ratings* operating temper ature range .................................................................................................... ............ 0 e c to +70 e c storage temperat ure ra nge ..................................................................................................... ........-55 e c to + 150 e c lead temperature range ......................................................................................... refer to jedec spec. j-std-020 positive voltage on any pin, with respec t to gr ound ........................................................................... ...........v cc + 0.3v negative voltage on any pin, with respec t to ground ........................................................................... ................. -0.3v maximum v cc ............................................................................................................................... ............................ +7v *stresses above those listed above could cause permanent dam age to the device. this is a stress rating only and functional operation of the device at any other condition above those indicat ed in the operation sections of this specification is not implied. note : when powering this device from laboratory or system power supplies, it is im portant that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addi tion, voltage transi ents on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. 6.2 dc electrical characteristics (t a = 0 e c - 70 e c, v cc = +5.0 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v ilck v ihck 3.0 0.4 v v input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 50 revision 1.0 (11-04-08) datasheet parameter symbol min typ max units comments o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc i/o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc i/o8 type buffer low output voltage high output voltage output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8 ma i oh = -4 ma v in = 0 to v cc o12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 12 ma i oh = -6 ma v in = 0 to v cc od16 type buffer low output level output leakage v ol i ol -10 0.5 +10 v a i ol = 16 ma v in = 0 to v cc supply current active supply current standby i cc i csby 60 8 95 ma ma all outputs open. capacitance t a = 25 e c; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground capacitive load on outputs ardy, d0-d15 240 pf all other outputs 45 pf
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 51 revision 1.0 (11-04-08) datasheet chapter 7 timing diagrams figure 7.1 - asynchronous cycle - nads=0 parameter min typ max units t1 a1-a15, aen, nbe0-nbe1 valid and nads low setup to nrd, nwr active 25 ns t2 a1-a15, aen, nbe0-nbe1 hold after nrd, nwr inactive (assuming nads tied low) 20 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns figure 7.2 - asynchronous cycle - using nads parameter min typ max units t1 a1-a15, aen, nbe0-nbe1 valid and nads low setup to nrd, nwr active 25 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t8 a1-a15, aen, nbe0-nbe1 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe1 hold after nads rising 15 ns t8 t9 t5 t3 t4 t1 t5a a1-a15, aen, nbe0-nbe1 valid d0-d15 valid address nads read data nrd, nwr write data a1-a15, aen, nbe0-nbe1 valid address t3 t4 nads read data t5 t5a d0-d15 valid write data t1 nrd, nwr t2
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 52 revision 1.0 (11-04-08) datasheet figure 7.3 ? address latching for all modes parameter min typ max units t8 a1-a15, aen, nbe0-nbe1 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe1 hold after nads rising 15 ns t25 a4-a15, aen to nldev delay 20 ns t8 t9 t25 a1-a15, aen, nbe0-nbe1 nads address nldev
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 53 revision 1.0 (11-04-08) datasheet figure 7.4 - sram interface parameter min typ max units t34 write ? ra2-ra16 setup to nrwe0-nrwe3 falling 0 ns t35 write ? ra2-ra16 hold after nrwe0-nrwe3 rising 0 ns t36 write ? rd0-rd31 setup to nrwe0-nrwe3 rising 12 ns t37 write ? rd0-rd31 hold after nrwe0-nrwe3 rising 0 ns t39 write ? nrwe0-nrwe3 pulse width 15 ns t54 write ? ra2-ra16 valid to end of write 12 ns t38 read ? ra2-ra16 valid to rd0-rd31 valid 15 ns t51 read ? rd0-rd31 hold after ra2-ra16 change 3 ns t52 read ? nroe enable to rd0-rd31 valid 12 ns t53 read ? nroe disable to rd0-rd31 invalid 0 8 ns t50 read/write ? cycle time 25 ns t53 t52 t37 t36 t39 t39 t50 t35 t54 t50 t34 t50 t51 t50 t38 read cycle write cycle ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31 t52 t38 t51 t38 t50 t51 t38 t50 t51 t38 multiple read cycles ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31 t53 t52 t37 t36 t39 t39 t50 t51 t50 t38 t50 t35 t54 t50 t34 read cycle write cycle ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 54 revision 1.0 (11-04-08) datasheet application note the following is the list of potential srams and suppliers for the lan91c110 rev b. these srams meet all timing requirements for lan91c110 rev b. but any other sram that meets the specificati on will also work with the lan91c110 rev b. min 3ns max 15ns min 25ns max 12ns max 8ns min 12ns min 12ns min 15ns manufacturer part # t51 data hold after address change t38 address valid to data valid r/w cycle output enable to output valid nroe disable to output in high z address valid to end of write data setup to end of write write pulse width issi is61c3216-10 3 10 10 5 5 9 5 7 issi is61c3216-12 3 12 12 5 6 10 6 8 issi is61c3216-15 3 15 15 7 7 11 7 10 alliance as7c256-12 3 12 12 5 3 8 6 8 alliance as7c256-15 3 15 15 6 4 10 8 9 winbond 24257aj-10 3 10 10 5 5 9 6 9 winbond 24257aj-12 3 12 12 6 6 10 7 10 cypress cy7c199-10vc 3 10 10 5 5 7 5 7 cypress cy7c199-12vc 3 12 12 5 5 9 8 8 cypress cy7c199-15vc 3 15 15 7 7 10 9 9 cypress cy7c1021-10 3 10 10 5 5 7 5 7 cypress cy7c1021-12 3 12 12 6 6 8 6 8 cypress cy7c1021-15 3 15 15 7 7 10 8 10 idt idt71016s12 4 12 12 7 6 9 7 9 idt idt71016s15 4 15 15 8 6 10 8 10 idt idt71256sa12 3 12 12 6 6 9 6 8 idt idt71256sa15 3 15 15 7 6 10 7 10 samsung k6e0808c1e-c10 3 10 10 5 5 8 5 8 samsung k6e0808c1e-c12 3 12 12 6 6 9 6 9 samsung k6e0808c1e-c15 3 15 15 7 7 10 7 10
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 55 revision 1.0 (11-04-08) datasheet t28 t28 t28 t27 t27 t29 t29 tx25 txd0-txd3 txen100 rxd0-rxd3 rx25 rx_dv rx_er figure 7.5 - mii interface parameter min typ max units t27 txd0-txd3, txen100 delay from tx25 rising 0 15 ns t28 rxd0-rxd3, rx_dv, rx_er setup to rx25 rising 10 ns t29 rxd0-rxd3, rx_dv, rx_er hold after rx25 rising 10 ns
feast fast ethernet controller for pcmcia and generic 16-bit applications datasheet smsc lan91c110 rev. b page 56 revision 1.0 (11-04-08) datasheet chapter 8 package outline figure 8.1 - 144 pin tqfp package outlines table 8.1 ? 144 pin tqfp package parameters min nominal max remark a ~ 1.0 1.20 overall package height a1 0.05 0.10 0.15 standoff a2 0.95 1.00 1.05 body thickness d 21.80 22.00 22.20 x span d/2 10.90 11.00 11.10 1 / 2 x span measure from centerline d1 19.80 20.00 20.20 x body size e 21.80 22.00 22.20 y span e/2 10.90 11.00 11.10 1 / 2 y span measure from centerline e1 19.80 20.00 20.20 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length from centerline l1 ~ 1.00 ~ lead length e 0.50 basic lead pitch 0 o 3.5 o 7 o lead foot angle w 0.13 0.18 0.23 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.0762 max coplanarity (assemblers) ccc ~ ~ 0.08 max coplanarity (test house) note 1: controlling unit: millimeter note 2: tolerance on the position of the leads is 0.04 mm maximum. note 3: package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. note 4: dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. note 5: details of pin 1 identifier are optional but must be located within the zone indicated.

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